The present invention pertains to a method and apparatus for source synchronous data transfer. More particularly, the present invention pertains to the transfer of data signals or the like from a first component with a clocking signal to a second component.
A bus is a common way to couple two or more components together to allow communication among them. A bus typically includes one or more signal lines that are coupled to each component. A signal line of the bus typically carries data, address, or control information (e.g., in a binary format).
A synchronous bus is one where components transmit and receive signals to/from the bus in synchronism with a common clock signal (e.g., a square wave with a 50% duty cycle). For example, a transmitting component may place data signals onto the bus at a time near the rising edge of a clock cycle, and a receiving component may receive and latch these data signals from the bus at a time near the rising edge of the next clock cycle. There are several problems present when using a synchronous bus. First, the conductors (e.g., conductive traces) between the common clock and the bus components may not be exactly matched. For example, the conductive traces may not have the same length. This leads to what is known in the art as clock skew, where a first component perceives a rising edge of the common clock at a different moment in time than a second component. Because of clock skew, tolerances must be built into a bus system to allow for the receiving component to receive data from a transmitting component over the bus at an appropriate time. One way to compensate for clock skew is to lower the bus clock frequency so that a large window of time is available for receiving signals from the bus.
In several known systems for transmitting signals between two components, the problem of clock skew is solved by providing a dedicated clock signal line between the components. For example, in one system, a dedicated clock signal line and dedicated data signal lines are provided for sending signals from a first component to a second component. Conversely, a different dedicated clock signal line and different dedicated data signal lines are provided for sending signals from the second component to the first component. The clock signals in this system are free-running clock signals that are continuously generated by the first and second components whether data signals are being transmitted or not. With this system, the first component drives data signals onto the dedicated signal line in relation to the clocking signal that appears on the clock signal line. The second component receives and latches the data signals at a point in time in relation to the same clocking signal. In another known system similar to the one described above, the dedicated data signal lines are combined to form a set of bidirectional data signal lines. Again, when a first component seeks to send data to a second component, it is done relative to the clock signal that is being continuously transmitted over the dedicated clock signal line.
The above described systems acceptably reduce clock skew for the transfer of data signals between two components. Expanding such systems to provide for the transfer of data signals among three or more components creates several problems. First, a dedicated clock signal would need to be provided between every two components which increases the number of connections (e.g., conductive traces) between components and the number of conductive input/output (I/O) pins needed on each component. Second, if the data signal lines are provided as a bus coupled to each component, then there is a problem of clock skew because the clock signal line and data signal lines between any two components may not match. Alternatively, dedicated data signal lines could be provided between every two components, however doing so would increase the number of connections between components and the number of conductive I/O pins needed on each component.
In view of the above, there is a need for a method and apparatus for transmitting data from one component to another that overcomes the above identified problems.